An intrinsic problem shared by all computer systems is the need for increased main memory system performance without a commensurate increase in energy consumption or cost. Electrical communication architectures struggle to balance the dichotomy for increased performance required of electronic systems while addressing lower power consumption, smaller form factor, and lower electromagnetic emissions. Better solutions dealing with scalability while reducing power consumption in computer systems are desirable. However, typical electronic solutions to these problems often increase the cost of the memory modules either because of increased pin count and/or die area, or increased power consumption, a major cause of which is the need to communicate over long wires.
A typical implementation example of a main memory system, in a computer system is one that can be implemented utilizing one or more dual in-line memory modules (“DIMMs”). A DIMM is a small circuit board that contains a number of discrete, dynamic random access memory (“DRAM”) chips that are connected to a memory controller using electronic interconnects forming one or more channels on a system board. There are many ways to increase main memory performance, such as increasing capacity, increasing the number of channels, increasing the number of DRAM banks or ranks, improving bandwidth, decreasing latency, or some combination of these ways. However, typical electronic solutions to these problems often increase the cost of the memory modules either because of increased pin count and/or die area, or increased power consumption. As mentioned above, a major cause of the increased power consumption is the need to communicate over long wires. Increasing the front side bus speed also causes a linear increase in interface power consumption. An additional interconnect issue with increasing the number of DIMM ranks at increased front side bus speeds is that both signal timing and noise are problems in the multi-drop wires that connect multiple DIMMs. This so called “stub electronics” problem has led to memory buses being replaced by point to point memory channels requiring additional external buffers to interface to the DRAMs. However, most DRAM efforts have focused on the creation of higher density memory devices with an electrical DIMM to processor chip interconnect rather than a DIMM replacement.
What is desired is a memory module architecture providing high speed, high bandwidth interconnects without the power and cost considerations of additional pins and long wires and which also maintains signal integrity.